1. Field of the Invention
This invention relates to an oscillation device and a display data processing device, and in particular, to an oscillation device and display data processing device capable of operating with lower power consumptions.
2. Related Art
A prior-art oscillation device will first of all be described. The configuration of a CR oscillator circuit that is a typical example of a prior-art oscillation device is shown in FIG. 34. Inverters 200, 201, 202, and 203 are connected in series, and a capacitor 204 is connected between the output of inverter 201 and the input of the inverter 200. A resistor 205 is connected between the output of the inverter 202 and the input of the inverter 200. The inverter 203 provides waveform shaping. As is well known, the oscillation frequency of a CR oscillator circuit with capacitance C and resistance R is given by: fOSC=1/(2.2.times.C.times.R). Note, however, that this does not include the intrinsic delays of the inverters 200, 201, and 202.
The configuration of a ring oscillator that is another example of a typical prior-art oscillation device is shown in FIG. 35. Inverters 207, 208, 209, and 210 are connected in series, with the output of the inverter 209 being fed back to the input of the inverter 207. The inverter 210 provides waveform shaping. As is well known, the oscillation frequency of a ring oscillator wherein the delay in each inverter is t(207), t(208), and t(209) is given by: fOSC=1/{2.times.[t(207)+t(208)+t(209)]}.
However, there are problems with the above described CR oscillation circuit and ring oscillator, as described below.
First of all, the duty ratio of both oscillation signals is close to 50% and it is not possible to adjust this duty ratio easily.
With a matrix display device or similar device, which is the main type of application of a display data processing device, the frequency for displaying one frame is called the frame frequency, where the rating for this frame frequency is generally in the range of 70 Hz to 130 Hz. Thus, in order to obtain this rating, it is necessary to ensure that the accuracy of the oscillation frequency of a CR oscillation circuit is within the range of .+-.30%. However, variations of 10% to 30% can occur in the capacitances and resistances of capacitors and resistors on a semiconductor substrate during the manufacture thereof. Thus it is impossible in practice to fabricate capacitors and resistors simultaneously on a semiconductor substrate, and also ensure an accurate oscillation frequency. Therefore, most of the resistors of CR oscillation circuits used in display data processing devices are components that are mounted separately.
The oscillation frequency of the clock that is necessary for the above described matrix display device is of the order of 10 kHz to 500 Hz. However, if an attempt is made to produce such a low-frequency oscillation with a ring oscillator, the circuitry becomes extremely big and an extremely large number of components are necessary. Therefore, a ring oscillator cannot be used in practice as an oscillation device in a matrix display device.
CR oscillation circuits that can vary the duty ratio of the oscillation signal are known, such as that shown in FIG. 36. This CR oscillation circuit has the configuration similar to that shown in FIG. 34, but with the addition of a resistor 211 and a diode 212. The duty ratio of this circuit can be controlled by adjusting the resistance ratio between the resistors 205 and 211. However, this CR oscillation circuit still has problems, as described below. First, the diode 212 has a parasitic resistance and capacitance, and a leakage current is generated when the diode 212 is reverse-biased. These parasitic resistance, parasitic capacitance, and leakage current have a huge adverse effect on oscillation signal generation and maintenance, and on the accuracy of the oscillation frequency. Secondly, it is difficult to form other circuits, such as the inverter 200, on the same semiconductor substrate as a diode that has favorable characteristics, and if such circuits somehow could be formed, the fabrication cost would be high. Thirdly, it is not possible to use a current source instead of the resistors 205 and 211 as means of modifying the duty ratio of this CR oscillation circuit. Fourthly, there is a problem in that it is not possible to make common the inverter 202 that is necessary for polarity inversion and the diode 212 that is necessary for switching.
It is clear from the above that there are various different problems with prior-art oscillation devices.
The description now turns to a prior-art display data processing device. An example of the configuration of a prior-art display data processing device is shown in FIG. 37A. This display data processing device comprises a plurality of memories for processing display data. In this case, a first memory 504, a second memory 506, and a storage device 508 may be equivalent to, for example, an image display memory, an image display pattern generator (such as a character generation read-only memory (CGROM) or character generation random-access memory (CGRAM)), and a line memory, respectively. A timing generation circuit 502 outputs first and second address signals 512 and 514 and first, second, and third signals 516, 518, and 520 thereto. The first and second signals 516 and 518 act as read signals for the first and second memories 504 and 506, and the third signal 520 acts as a write signal for the storage device 508. A clock signal CK 510 from an oscillation device 500 is supplied to the timing generation circuit 502 and the timing generation circuit 502 generates various signals based on the clock signal CK 510, as shown in FIG. 37B. An address for the second memory 506 is generated in this display data processing device based on first data 522 that is an output of the first memory 504, then second data 524 that is an output of the second memory 506 is written to the storage device 508.
As shown in FIG. 37B, when a first signal 516 goes low (point F in FIG. 37B), a read operation of the first memory 504 starts and the first data 522 is read out. Since an address for the second memory 506 will be generated based on this first data 522, it is necessary for a second signal 518 to fall at least one clock later than the first signal 516 (point G). When the second signal 518 goes low, the second data 524 is output from the second memory 506. Since the storage device 508 will store this second data 524, it is necessary for the third signal 520 to fall at least one clock later than the second signal 518 (point H). The timing generation circuit 502 raises the first to third signals 516 to 520 to high when the data write to the storage device 508 ends.
With the above described prior-art display data processing device, signals of various different timings have to be generated by the timing generation circuit 502 to take into account the access times of the first and second memories and the storage device. Thus, as is clear from FIG. 37B, it is necessary to use a clock signal CK that has a frequency three to five times that of the first to third signals, to generate these signals, making it difficult to reduce the overall power consumption.
It is also possible to use devices such as a delay circuit based on a clock signal of the same frequency as the first to third signals, to generate the various timing signals shown in FIG. 37B. However, variations in quality due to the fabrication process make it extremely difficult to generate these signals while taking into account factors such as the access times of the first and second memories and the storage device. It is thus desirable to provide a display data processing device that can adjust autonomously timing between the first and second memories and the storage means,
This invention was devised in order to solve the above concerns and has as its objective the provision of an oscillation device and a display data processing device that implements reductions in power consumption and circuit size.
Another objective of this invention is to provide an oscillation device that enables highly accurate, but simple, adjustment of the oscillation frequency and duty ratio of the oscillation signal.
A further objective of this invention is to provide a display data processing device having a plurality of memories, wherein the display data processing device enables autonomous control over the adjustment of timings between the memories.